Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 353 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 10-7
Watchdog Timer
Watchdog Control (WDOG_CTL) Register
The
WDOG_CTL
register, shown in Figure 10-4 , is a 16-bit system MMR
used to control the watchdog timer.
The watchdog event (
WDEV[1:0]
) bit field is used to select the event that is
generated when the watchdog timer expires. Note that if the general-pur-
pose interrupt option is selected, the
SIC_IMASK
register that holds the
watchdog timer mask bit should be appropriately configured to unmask
that interrupt. If the generation of watchdog events is disabled, the watch-
dog timer operates as described, except that no event is generated when
the watchdog timer expires.
The watchdog enable (
WDEN[7:0]
) bit field is used to enable and disable
the watchdog timer. Writing any value other than the disable key (0xAD)
into this field enables the watchdog timer. This multibit disable key mini-
mizes the chance of inadvertently disabling the watchdog timer.
Software can determine whether the watchdog has expired by interrogat-
ing the
WDRO
status bit of the
WDOG_CTL
register. This is a sticky bit that is
set whenever the watchdog timer count reaches 0. It can be cleared only by
writing a “1” to the bit when the watchdog has been disabled first.
Figure 10-3. Watchdog Status Register
Watchdog S tatus Register (WDOG_ S TAT)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reset = 0x0000 0000
Watchdog S tatus[ 3 1:16]
Watchdog S tatus[15:0]