Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 50 / 772

Two-Wire Interface
1-8 ADSP-BF59x Blackfin Processor Hardware Reference
• GPIO interrupt mask registers – The two GPIO interrupt mask
registers allow each individual GPIO pin to function as an inter-
rupt to the processor. Similar to the two GPIO control registers
that are used to set and clear individual pin values, one GPIO
interrupt mask register sets bits to enable interrupt function, and
the other GPIO interrupt mask register clears bits to disable inter-
rupt function. GPIO pins defined as inputs can be configured to
generate hardware interrupts, while output pins can be triggered by
software interrupts.
• GPIO interrupt sensitivity registers – The two GPIO interrupt sen-
sitivity registers specify whether individual pins are level- or
edge-sensitive and specify—if edge-sensitive—whether just the ris-
ing edge or both the rising and falling edges of the signal are
significant. One register selects the type of sensitivity, and one reg-
ister selects which edges are significant for edge-sensitivity.
Two-Wire Interface
The Two-Wire Interface (TWI) is compatible with the widely used I
2
C
bus standard. It was designed with a high level of functionality and is
compatible with multi-master, multi-slave bus configurations. To preserve
processor bandwidth, the TWI controller can be set up and a transfer ini-
tiated with interrupts only to service FIFO buffer data reads and writes.
Protocol related interrupts are optional.
The TWI externally moves 8-bit data while maintaining compliance with
the I
2
C bus protocol. The Philips I
2
C Bus Specification version 2.1 covers
many variants of I
2
C. The TWI controller includes these features:
• Simultaneous master and slave operation on multiple device
systems
• Support for multi-master data arbitration