Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 670 / 772

Specific Boot Modes
16-48 ADSP-BF59x Blackfin Processor Hardware Reference
The Timer1 is configured to generate a periodic pulse as opposed to a sin-
gle shot pulse. The pulse period is set to the maximum of 0xFFFFFFFF
allowing for any transfer size supported by the kernel. Note the current
16-bit DMA X Count limits the maximum width of a pulse to 0xFFFF
words.
After completion of the DMA transfer, the
PWM_OUT
out mode is termi-
nated and cleared in the required manner. This mode of operation does
impose some restrictions on the amount of time that the PPI host device
can hold off a transfer. If a DMA transfer consists of 0xFFFF words, the
timer period will be reached 0xFFFF0000
PPI_CLK
cycles after the
de-assertion of the
PPI_FS2
/TMR1 signal. This will result in the genera-
tion of an identical
PPI_FS2
/TMR1 pulse if the DMA transfer has not
completed and the
PWM_OUT
timer has not been disabled.
In the unlikely event that a user requires a transfer to be held off for this
significant amount of time, the PPI host must be able to ignore any fur-
ther
PPI_FS2
/TMR1 assertions until the currently pending transaction
that was delayed has completed. If the master is not capable of ignoring
further
PPI_FS2
/TMR1 assertions, the master must ensure that the DMA
completes allowing for the
PWM_OUT
timer to be disabled prior to the com-
pletion of the timer pulse period of 0xFFFFFFFF
PPI_CLK
cycles.
Figure 16-15. PPI Slave Boot Mode Connections
(MASTER PPI DEVICE)
BLACKFIN
PPI_CLK PPI_CLK
HOST
(SLAVE PPI DEVICE)
PPI_FS1 PPI_FS1
PPI_FS2 PPI_FS2
PPI_DATA15-0
PPI_DATA15-0
VDDEXT
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