Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 475 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 13-21
SPI-Compatible Port Controller
Slave Ready for a Transfer
When a device is enabled as a slave, the actions shown in Table 13-2 are
necessary to prepare the device for a new transfer.
Programming Model
The following sections describe the SPI programming model.
Beginning and Ending an SPI Transfer
The start and finish of an SPI transfer depend on whether the device is
configured as a master or a slave, which
CPHA
mode is selected, and which
transfer initiation mode (
TIMOD
) is selected. For a master SPI with
CPHA
= 0, a transfer starts when either
SPI_TDBR
is written to or
SPI_RDBR
is read, depending on
TIMOD
. At the start of the transfer, the enabled slave
select outputs are driven active (low). However, the
SCK
signal remains
inactive for the first half of the first cycle of
SCK
. For a slave with
CPHA
= 0,
the transfer starts as soon as the
SPISS
input goes low.
For
CPHA
= 1, a transfer starts with the first active edge of
SCK
for both
slave and master devices. For a master device, a transfer is considered
Table 13-2. Transfer Preparation
TIMOD Function Action, Interrupt
b#00 Transmit and
receive Interrupt is active when the receive buffer is full.
Read of SPI_RDBR clears interrupt.
b#01 Transmit and
receive Interrupt is active when the transmit buffer is empty.
Writing to SPI_TDBR clears interrupt.
b#10 Receive with
DMA Request DMA reads as long as SPI DMA FIFO is not empty.
b#11 Transmit with
DMA Request DMA writes as long as SPI DMA FIFO is not full.