Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 417 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 12-19
Two Wire Interface Controller
Clock Stretching During FIFO Overflow
During a master mode receive, an interrupt is generated at the instant the
receive FIFO becomes full. It is during the acknowledge phase of this
received byte that clock stretching begins. No attempt is made to initiate
the reception of an additional byte. Stretching of the clock continues until
the data bytes previously received are read from the receive FIFO buffer
(
TWI_RCV_DATA8
,
TWI_RCV_DATA16
). No other action is required to release
the clock and continue the reception of data. This behavior continues
until the reception is complete (
DCNT
= 0x00) at which time the reception
is concluded (
MCOMP
) as shown in Figure 12-10 and described in
Table 12-6 .
Figure 12-10. Clock Stretching During FIFO Overflow
Table 12-6. FIFO Overflow Case
TWI Controller Processor
Interrupt: RCVSERV – Receive FIFO buffer is
full. Acknowledge: Clear interrupt source bits.
Read receive FIFO buffer.
... ...
Interrupt: MCOMP – Master receive complete. Acknowledge: Clear interrupt source bits.
S ADDRESS DATA
ACK WITH
STRETCH
ACK R/W DATA ACK DATA
00 01 11
RCVSTAT[1:0]
TWI_RCV_DATA IS READ AT THIS TIME AND
CLOCK STRETCHING IS RELEASED.
ACKNOWLEDGE WITH STRETCH
00
SCL
ACKNOWLEDGE "STRETCH" BEGINS SOON AFTER SCL FALL.