Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 383 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 11-27
UART Port Controllers
appropriate interrupt handling routines must be present. For backward
compatibility, the
UART_IIR
still reflects the correct interrupt status.

Each UART features three separate interrupt channels to handle
data transmit, data receive, and line status events independently,
regardless of whether DMA is enabled or not. On some processors,
the status interrupt channels from multiple UARTs may be ORed
prior to being connected to the system interrupt controller. See
Chapter 4, “System Interrupts” for more information.
With system DMA enabled, the UART uses DMA to transfer data to or
from the processor. Dedicated DMA channels are available to receive and
transmit operation. Line error handling can be configured completely
independently from the receive/transmit setup.
The
UART_IER
registers are mapped to the same address as the
UART_DLH
registers. To access
UART_IER
, the
DLAB
bit in
UART_LCR
must be cleared.
The UART’s DMA is enabled by first setting up the system DMA control
registers and then enabling the UART
ERBFI
and/or
ETBEI
interrupts in
the
UART_IER
register. This is because the interrupt request lines double as
Figure 11-12. UART Interrupt Enable Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ERBFI (Enable Receive
Buffer Full Interrupt)
UART Interrupt Enable Register (UART_IER)
ETBEI (Enable Transmit
Buffer Empty Interrupt)
EL S I (Enable RX S tatus Interrupt)
0 - No interrupt
1 - Generate RX interrupt if
DR bit in UART_LSR is
set
0 - No interrupt
1 - Generate TX interrupt if
THRE bit in UART_LSR is
set
0 - No interrupt
1 - Generate line status interrupt if
any of UART_LSR[4:1] is set
Reset = 0x0000