Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 528 / 772

Description of Operation
14-22 ADSP-BF59x Blackfin Processor Hardware Reference
When the frame sync/data relationship is used (
FSDR
= 1), the frame sync
is expected to change on the falling edge of the clock and is sampled on
the rising edge of the clock. This is true even though data received is sam-
pled on the negative edge of the receive clock.
Channel Selection Register
A channel is a multibit word from 3 to 32 bits in length that belongs to
one of the TDM channels. Specific channels can be individually enabled
or disabled to select which words are received and transmitted during mul-
tichannel communications. Data words from the enabled channels are
received or transmitted, while disabled channel words are ignored. Up to
128 contiguous channels may be selected out of 1024 available channels.
The
SPORT_MRCSn
and
SPORT_MTCSn
multichannel select registers are used
to enable and disable individual channels; the
SPORT_MRCSn
registers spec-
ify the active receive channels, and the
SPORT_MTCSn
registers specify the
active transmit channels.
Four registers make up each multichannel select register. Each of the four
registers has 32 bits, corresponding to 32 channels. Setting a bit enables
that channel, so the SPORT selects its word from the multiple word block
of data (for either receive or transmit). See
Figure 14-8 .
Channel select bit 0 always corresponds to the first word of the active win-
dow. To determine a channel’s absolute position in the frame, add the
window offset words to the channel select position. For example, setting
bit 7 in
MCS2
selects word 71 of the active window to be enabled. Setting
bit 2 in
MCS1
selects word 34 of the active window, and so on.
Figure 14-8. Multichannel Select Registers
CHANNEL SELECT 0-127
MCS0 MCS1 MCS2 MCS3
0
0
31
31 0 31 0 31 0 31
32 63 64 95 96 127