Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 170 / 772

DMA Registers
5-70 ADSP-BF59x Blackfin Processor Hardware Reference
•
DMA2D
(DMA mode). This bit specifies whether DMA mode
involves only
DMAx_X_COUNT
and
DMAx_X_MODIFY
(one-dimensional
DMA) or also involves
DMAx_Y_COUNT
and
DMAx_Y_MODIFY
(two-dimensional DMA).
•
WDSIZE[1:0]
(transfer word size). The DMA engine supports trans-
fers of 8-, 16-, or 32-bit items. Each request/grant results in a
single memory access (although two cycles are required to transfer
32-bit data through a 16-bit memory port or through the 16-bit
DMA access bus). The increment sizes (strides) of the DMA
address pointer registers must be a multiple of the transfer unit
size—one for 8-bit, two for 16-bit, four for 32-bit.
Only SPORT DMA and Memory DMA can operate with a transfer
size of 32 bits. All other peripherals have a maximum DMA trans-
fer size of 16 bits.
•
WNR
(DMA direction). This bit specifies DMA direction—memory
read (0) or memory write (1).
•
DMAEN
(DMA channel enable). This bit specifies whether to enable
a given DMA channel.

When a peripheral DMA channel is enabled, interrupts from the
peripheral denote DMA requests. When a channel is disabled, the
DMA unit ignores the peripheral interrupt and passes it directly to
the interrupt controller. To avoid unexpected results, take care to
enable the DMA channel before enabling the peripheral, and to
disable the peripheral before disabling the DMA channel.