Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 729 / 772

ADSP-BF59x Blackfin Processor Hardware Reference A-19
System MMR Assignments
TWI Registers
Two Wire Interface (TWI) registers (0xFFC0 1400 – 0xFFC0 14FF) are
listed in
Table A-19 .
Table A-19. TWI Registers
Memory-Mapped
Address Register Name For individual bits, see this diagram:
0xFFC0 1400 TWI_CLKDIV “SCL Clock Divider Register (TWI_CLKDIV)” on
page 12-25
0xFFC0 1404 TWI_CONTROL “TWI CONTROL Register (TWI_CONTROL)”
on page 12-24
0xFFC0 1408 TWI_SLAVE_CTL “TWI Slave Mode Control Register
(TWI_SLAVE_CTL)” on page 12-26
0xFFC0 140C TWI_SLAVE_STAT “TWI Slave Mode Status Register
(TWI_SLAVE_STAT)” on page 12-28
0xFFC0 1410 TWI_SLAVE_ADDR “TWI Slave Mode Address Register
(TWI_SLAVE_ADDR)” on page 12-28
0xFFC0 1414 TWI_MASTER_CTL “TWI Master Mode Control Register
(TWI_MASTER_CTL)” on page 12-29
0xFFC0 1418 TWI_MASTER_STAT “TWI Master Mode Status Register
(TWI_MASTER_STAT)” on page 12-33
0xFFC0 141C TWI_MASTER_ADDR “TWI Master Mode Address Register
(TWI_MASTER_ADDR)” on page 12-32
0xFFC0 1420 TWI_INT_STAT “TWI Interrupt Status Register
(TWI_INT_STAT)” on page 12-40
0xFFC0 1424 TWI_INT_MASK “TWI Interrupt Mask Register
(TWI_INT_MASK)” on page 12-39
0xFFC0 1428 TWI_FIFO_CTL “TWI FIFO Control Register (TWI_FIFO_CTL)”
on page 12-36
0xFFC0 142C TWI_FIFO_STAT “TWI FIFO Status Register (TWI_FIFO_STAT)”
on page 12-38
0xFFC0 1480 TWI_XMT_DATA8 “TWI FIFO Transmit Data Single Byte Register
(TWI_XMT_DATA8)” on page 12-43