Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 81 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 3-7
Chip Bus Hierarchy
DAB Bus Agents (Masters)
All peripherals capable of sourcing a DMA access are masters on this bus,
as shown in
Table 3-1 . A single arbiter supports a programmable priority
arbitration policy for access to the DAB.
When two or more DMA master channels are actively requesting the
DAB, bus utilization is considerably higher due to the DAB’s pipelined
design. Bus arbitration cycles are concurrent with the previous DMA
access’s data cycles.
SPORT0 transmit 2
SPORT1 receive 3
SPORT1 transmit 4
SPI0 transmit/receive 5
SPI1 transmit/receive 6
UART0 receive 7
UART0 transmit 8
Not available on this product 9
Not available on this product 10
Not available on this product 11
Mem DMA has no peripheral mapping. 12
Mem DMA has no peripheral mapping. 13
Mem DMA has no peripheral mapping. 14
Mem DMA has no peripheral mapping. 15 - lowest
Table 3-1. DAB and DCB Arbitration Priority (Continued)
DAB, DCB Master Default Arbitration Priority