Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 425 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 12-27
Two Wire Interface Controller
Additional information for the
TWI_SLAVE_CTL
register bits includes:
• General call enable (
GEN
)
General call address detection is available only when slave mode is
enabled.
[0] General call address matching is not enabled.
[1] General call address matching is enabled. A general call slave
receive transfer is accepted. All status and interrupt source bits
associated with transfers are updated.
• NAK (
NAK
)
[0] Slave receive transfers generate an ACK at the conclusion of a
data transfer.
[1] Slave receive transfers generate a data NAK (not acknowledge)
at the conclusion of a data transfer. The slave is still considered to
be addressed.
• Slave transmit data valid (
STDVAL
)
[0] Data in the transmit FIFO is for master mode transmits and is
not allowed to be used during a slave transmit, and the transmit
FIFO is treated as if it is empty.
[1] Data in the transmit FIFO is available for a slave transmission.
• Slave enable (
SEN
)
[0] The slave is not enabled. No attempt is made to identify a valid
address. If cleared during a valid transfer, clock stretching ceases,
the serial data line is released, and the current byte is not
acknowledged.
[1] The slave is enabled. Enabling slave and master modes of oper-
ation concurrently is allowed.