Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 574 / 772

Programming Examples
14-68 ADSP-BF59x Blackfin Processor Hardware Reference
Because of the many possible configurations, the example uses generic
labels for the content of the SPORT’s configuration registers (
SPORT_RCRn
and
SPORT_TCRn
) and the DMA configuration. An example value is given
in the comments, but for the meaning of the individual bits the user is
referred to the detailed explanation in this chapter.
The example configures both the receive and the transmit section. Since
they are completely independent, the code uses separate labels.
SPORT Initialization Sequence
The SPORT’s receiver and transmitter are configured, but they are not
enabled yet.
Listing 14-1. SPORT Initialization
Program_SPORT_TRANSMITTER_Registers:
/* Set P0 to SPORT0 Base Address */
P0.h = hi(SPORT0_TCR1);
P0.l = lo(SPORT0_TCR1);
/* Configure Clock speeds */
R1 = SPORT_TCLK_CONFIG; /* Divider SCLK/TCLK (value 0 to
65535) */
W[P0 + (SPORT0_TCLKDIV - SPORT0_TCR1)] = R1;
/* TCK divider register */
/* number of Bitclocks between FrameSyncs -1 (value SPORT_SLEN
to 65535) */
R1 = SPORT_TFSDIV_CONFIG;
W[P0 + (SPORT0_TFSDIV - SPORT0_TCR1)] = R1;
/* TFSDIV register */
/* Transmit configuration */
/* Configuration register 2 (for instance 0x000E for 16-bit
wordlength) */
R1 = SPORT_TRANSMIT_CONF_2;