Functional Description
5-26
ADSP-BF59x Blackfin Processor Hardware Reference
is indicated by the
DMA_RUN
bit in the
DMAx_IRQ_STATUS
register; if it is 1,
the FIFO is not empty yet. Do not start a new work unit with different
word size or direction while
DMA_RUN
= 1. Further, if the channel is dis-
abled (by writing
DMAEN
= 0), the data in the FIFO is lost.
SYNC
= 1 selects a synchronized transition in which the DMA FIFO is first
drained to the destination memory or peripheral before any interrupt is
signalled and before any subsequent descriptor or data is fetched. This
incurs greater latency, but provides direct synchronization between the
DMA interrupt and the state of the data at the peripheral.
For example, if
SYNC
= 1 and
DI_EN
= 1 on the last descriptor in a work
unit, the interrupt occurs when the final data has been transferred to the
peripheral, allowing the service routine to properly switch to non-DMA
transmit operation. When the interrupt service routine is invoked, the
DMA_DONE
bit is set and the
DMA_RUN
bit is cleared.
A synchronized transition also allows greater flexibility in the format of
the DMA descriptor chain. If
SYNC
= 1, the next descriptor may have any
word size or read/write direction supported by the peripheral and may
come from either memory space (internal or external). This can be useful
in managing MDMA work unit queues, since it is no longer necessary to
interrupt the queue between dissimilar work units.
DMA Receive
In DMA receive (memory write) channels, the
SYNC
bit controls the han-
dling of the DMA FIFO between descriptor chains (not individual
descriptors), when the DMA channel is paused. The DMA channel pauses
after descriptors with
FLOW
= 0 mode, and may be restarted (for example,
after an interrupt) by writing the channel’s
DMAx_CONFIG
register with
DMAEN
= 1.
If the
SYNC
bit is 0 in the new work unit’s
DMAx_CONFIG
value, a continuous
transition is selected. In this mode, any data items received into the DMA
FIFO while the channel was paused are retained, and they are the first
Summary of Contents for ADSP-BF59x Blackfin
Page 64: ...Development Tools 1 22 ADSP BF59x Blackfin Processor Hardware Reference...
Page 74: ...Processor Specific MMRs 2 10 ADSP BF59x Blackfin Processor Hardware Reference...
Page 244: ...Programming Examples 6 40 ADSP BF59x Blackfin Processor Hardware Reference...
Page 700: ...Programming Examples 16 78 ADSP BF59x Blackfin Processor Hardware Reference...
Page 738: ...Boundary Scan Architecture B 8 ADSP BF59x Blackfin Processor Hardware Reference...