Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 459 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 13-5
SPI-Compatible Port Controller
The
SCK
is used to shift out and shift in the data driven on the
MISO
and
MOSI
lines. Clock polarity and clock phase relative to data are programma-
ble in the
SPI_CTL
register and define the transfer format.
Master-Out, Slave-In (MOSI) Signal
The master-out, slave-in (
MOSI
) signal is one of the bidirectional I/O data
pins. If the processor is configured as a master, the
MOSI
pin transmits data
out. If the processor is configured as a slave, the
MOSI
pin receives data in.
In an SPI interconnection, the data is shifted out from the
MOSI
output
pin of the master and shifted into the
MOSI
input(s) of the slave(s).
Master-In, Slave-Out (MISO) Signal
The master-in, slave-out (
MISO
) signal is one of the bidirectional I/O data
pins. If the processor is configured as a master, the
MISO
pin receives data
in. If the processor is configured as a slave, the
MISO
pin transmits data
out. In an SPI interconnection, the data is shifted out from the
MISO
out-
put pin of the slave and shifted into the
MISO
input pin of the master.

Only one slave is allowed to transmit data at any given time.
The SPI configuration example in Figure 13-2 illustrates how the proces-
sor can be used as the slave SPI device. The 8-bit host microcontroller is
the SPI master.

The processor can be booted through its SPI interface to allow user
application code and data to be downloaded before runtime.