DMA Registers
5-80
ADSP-BF59x Blackfin Processor Hardware Reference
DMA Next Descriptor Pointer Registers
(DMAx_NEXT_DESC_PTR/
MDMA_yy_NEXT_DESC_PTR)
The 32-bit
DMAx_NEXT_DESC_PTR
register, shown in
Figure 5-16
, specifies
where to look for the start of the next descriptor block when the DMA
activity specified by the current descriptor block finishes. This register is
used in small and large descriptor list modes. At the start of a descriptor
fetch in either of these modes, this register is copied into the
DMAx_CURR_DESC_PTR
register. Then, during the descriptor fetch, the
DMAx_CURR_DESC_PTR
register increments after each element of the descrip-
tor is read in.
In small and large descriptor list modes, the
DMAx_NEXT_DESC_PTR
register, and not the
DMAx_CURR_DESC_PTR
register, must be pro-
grammed directly via MMR access before starting DMA operation.
In descriptor array mode, the next descriptor pointer register is disre-
garded, and fetching is controlled only by the
DMAx_CURR_DESC_PTR
register.
Figure 5-16. DMA Next Descriptor Pointer Registers
31 30
29 28
27 26
25 24
23 22
21 20
19
18
17 16
X
Next Descriptor
Pointer[
3
1:16]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DMA Next Descriptor Pointer Registers
(DMAx_NEXT_DE
S
C_PTR/MDMA_yy_NEXT_DE
S
C_PTR)
R/W prior to enabling channel; RO after enabling channel
15 14
13 12
11 10
9
8
7
6
5
4
3
2
1
0
X
Next Descriptor
Pointer[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Reset = Undefined
Summary of Contents for ADSP-BF59x Blackfin
Page 64: ...Development Tools 1 22 ADSP BF59x Blackfin Processor Hardware Reference...
Page 74: ...Processor Specific MMRs 2 10 ADSP BF59x Blackfin Processor Hardware Reference...
Page 244: ...Programming Examples 6 40 ADSP BF59x Blackfin Processor Hardware Reference...
Page 700: ...Programming Examples 16 78 ADSP BF59x Blackfin Processor Hardware Reference...
Page 738: ...Boundary Scan Architecture B 8 ADSP BF59x Blackfin Processor Hardware Reference...