
ADSP-BF59x Blackfin Processor Hardware Reference
5-59
Direct Memory Access
have no interrupt enable set, while the last active descriptor contains a
FLOW
of 0 and an interrupt enable bit
DI_EN
set to 1. Also, all but the last
waiting descriptors contain
FLOW
values
≥
4 and no interrupt enables set,
while the last waiting descriptor contains a
FLOW
of 0 and an interrupt
enable bit set. This ensures that the DMA unit can automatically process
the whole active queue and then issue one interrupt. Also, this arrange-
ment makes it easy to start the waiting queue within the interrupt handler
with a single
DMAx_CONFIG
register write.
After queuing a new waiting descriptor, the non-interrupt software should
leave a message for its interrupt handler in a memory mailbox location
containing the desired
DMAx_CONFIG
value to use to start the first waiting
descriptor in the waiting queue (or 0 to indicate no descriptors are
waiting).
Once processing by the DMA unit has started, it is critical that the soft-
ware not directly modify the contents of the active descriptor queue unless
careful synchronization measures are taken. In the most straightforward
implementation of a descriptor queue, the DMA manager software would
never modify descriptors on the active queue; instead, the DMA manager
waits until the DMA queue completion interrupt indicates the processing
of the entire active queue is complete.
When a DMA queue completion interrupt is received, the interrupt han-
dler reads the mailbox from the non-interrupt software and writes the
value in it to the DMA channel’s
DMAx_CONFIG
register. This single register
write restarts the queue, effectively transforming the waiting queue to an
active queue. The interrupt handler should then pass a message back to
the non-interrupt software indicating the location of the last descriptor
accepted into the active queue. If, on the other hand, the interrupt han-
dler reads its mailbox and finds a
DMAx_CONFIG
value of zero, indicating
there is no more work to perform, then it should pass an appropriate mes-
sage (for example zero) back to the non-interrupt software indicating that
the queue has stopped. This simple handler should be able to be coded in
a very small number of instructions.
Summary of Contents for ADSP-BF59x Blackfin
Page 64: ...Development Tools 1 22 ADSP BF59x Blackfin Processor Hardware Reference...
Page 74: ...Processor Specific MMRs 2 10 ADSP BF59x Blackfin Processor Hardware Reference...
Page 244: ...Programming Examples 6 40 ADSP BF59x Blackfin Processor Hardware Reference...
Page 700: ...Programming Examples 16 78 ADSP BF59x Blackfin Processor Hardware Reference...
Page 738: ...Boundary Scan Architecture B 8 ADSP BF59x Blackfin Processor Hardware Reference...