Unique Information for the ADSP-BF59x Processor
4-18
ADSP-BF59x Blackfin Processor Hardware Reference
20
Bit 20
SIC_IAR2[19:16]
GP Timer 1
IVG11
19
Bit 19
SIC_IAR2[15:12]
GP Timer 0
IVG11
18
Bit 18
SIC_IAR2[11:8]
Port F Interrupt B
IVG11
17
Bit 17
SIC_IAR2[7:4]
Port F Interrupt A
IVG11
16
Bit 16
SIC_IAR2[3:0]
DMA8 (UART0 TX)
IVG10
15
Bit 15
SIC_IAR1[31:28]
DMA7 (UART0 RX)
IVG10
14
Bit 14
SIC_IAR1[27:24]
DMA6 (SPI1 RX/TX)
IVG10
13
Bit 13
SIC_IAR1[23:20]
DMA5 (SPI0 RX/TX)
IVG10
12
Bit 12
SIC_IAR1[19:16]
DMA4 (SPORT1 TX)
IVG9
11
Bit 11
SIC_IAR1[15:12]
DMA3 (SPORT1 RX)
IVG9
10
Bit 10
SIC_IAR1[11:8]
DMA2 (SPORT0 TX)
IVG9
9
Bit 9
SIC_IAR1[7:4]
DMA1 (SPORT0 RX)
IVG9
8
Bit 8
SIC_IAR1[3:0]
DMA0 (PPI)
IVG8
7
Bit 7
SIC_IAR0[31:28]
UART0 Status
IVG7
6
Bit 6
SIC_IAR0[27:24]
SPI1 Status
IVG7
5
Bit 5
SIC_IAR0[23:20]
SPI0 Status
IVG7
4
Bit 4
SIC_IAR0[19:16]
SPORT1 Status
IVG7
3
Bit 3
SIC_IAR0[15:12]
SPORT0 Status
IVG7
2
Bit 2
SIC_IAR0[11:8]
PPI Status
IVG7
1
Bit 1
SIC_IAR0[7:4]
DMA Error (generic)
IVG7
0
Bit 0
SIC_IAR0[3:0]
PLL Wakeup
IVG7
Table 4-3. Peripheral Interrupt Events (Continued)
Peripheral
ID Number
Bit Position for
SIC_ISR0,
SIC_IMASK0,
SIC_IWR0
SIC_IAR3-0
Interrupt Source
Default
Mapping
Summary of Contents for ADSP-BF59x Blackfin
Page 64: ...Development Tools 1 22 ADSP BF59x Blackfin Processor Hardware Reference...
Page 74: ...Processor Specific MMRs 2 10 ADSP BF59x Blackfin Processor Hardware Reference...
Page 244: ...Programming Examples 6 40 ADSP BF59x Blackfin Processor Hardware Reference...
Page 700: ...Programming Examples 16 78 ADSP BF59x Blackfin Processor Hardware Reference...
Page 738: ...Boundary Scan Architecture B 8 ADSP BF59x Blackfin Processor Hardware Reference...