Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 210 / 772

Phase Locked Loop and Clock Control
6-6 ADSP-BF59x Blackfin Processor Hardware Reference
As long as the
MSEL
and
DF
control bits in the PLL control (
PLL_CTL
) regis-
ter remain constant, the PLL is locked.

If changing the clock ratio via writing a new
SSEL
value into
PLL_DIV
, take care that the enabled peripherals do not suffer data
loss due to
SCLK
frequency changes.
When changing clock frequencies in the PLL, the PLL requires time to
stabilize and lock to the new frequency. The PLL lock count
(
PLL_LOCKCNT
) register defines the number of
CLKIN
cycles that occur
before the processor sets the
PLL_LOCKED
bit in the
PLL_STAT
register.
When executing the PLL programming sequence, the internal PLL lock
counter begins incrementing upon execution of the
IDLE
instruction. The
lock counter increments by 1 each
CLKIN
cycle. When the lock counter has
incremented to the value defined in the
PLL_LOCKCNT
register, the
PLL_LOCKED
bit is set.
See the processor data sheet for more information about PLL stabilization
time and programmed values for this register. For more information about
operating modes, see
“Operating Modes” on page 6-7 .
Table 6-3. System Clock Ratio
Signal Name
SSEL[3:0] Divider Ratio
VCO/SCLK Example Frequency Ratios (MHz)
VCO
SCLK
0000 Reserved N/A N/A
0001 1:1 50 50
0010 2:1 150 75
0011 3:1 150 50
0100 4:1 200 50
0101 5:1 300 60
0110 6:1 360 60
N = 7–15 N:1 400 400/N