Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 201 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 5-101
Direct Memory Access
CC = r1 < r0;
if CC jump initial_requests;
/* disable and reenable to clear edge count */
p1.l = lo(HMDMA1_CONTROL);
r0.l = 0;
w[p1] = r0;
w[p1] = r2;
If the polling operation shown in Listing 5-9 is too expensive, an interrupt
version of it can be implemented by using the HMDMA overflow feature.
Temporarily set the
HMDMAx_OVERFLOW
register to eight.
Unique Information for the ADSP-BF59x
Processor
Figure 5-28 on page 5-102 provides a block diagram of the ADSP-BF59x
DMA controller.

The ADSP-BF59x processors do not contain either cache, an asyn-
chronous memory interface, an SDRAM interface, or an HMDMA
controller. Therefore, any discussion or examples above regarding
cache, asynchronous memory, SDRAM, and HMDMA do
not
apply to the ADSP-BF59x.
Static Channel Prioritization
The default DMA channel priority and mapping shown in Table 5-9 on
page 5-103 can be changed by altering the 4-bit PMAP field in the
DMAx_PERIPHERAL_MAP
registers for the peripheral DMA channels.