Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 515 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 14-9
SPORT Controller
Description of Operation
This section describes general SPORT operation, illustrating the most
common use of a SPORT. Since the SPORT functionality is configurable,
this description represents just one of many possible configurations.
Writing to a
SPORT_TX
register readies the SPORT for transmission. The
TFS
signal initiates the transmission of serial data. Once transmission has
begun, each value written to the
SPORT_TX
register is transferred through
the FIFO to the internal transmit shift register. The bits are then sent,
beginning with either the MSB or the LSB as specified in the
SPORT_TCR1
register. Each bit is shifted out on the driving edge of
TSCLK
. The driving
edge of
TSCLK
can be configured to be rising or falling. The SPORT gener-
ates the transmit interrupt or requests a DMA transfer as long as there is
space in the TX FIFO.
As a SPORT receives bits, they accumulate in an internal receive register.
When a complete word has been received, it is written to the SPORT
FIFO register and the receive interrupt for that SPORT is generated or a
DMA transfer is initiated. Interrupts are generated differently if DMA
block transfers are performed.
SPORT Disable
The SPORTs are automatically disabled by a processor hardware or soft-
ware reset. A SPORT can also be disabled directly by clearing the
SPORT’s transmit or receive enable bits (
TSPEN
in the
SPORT_TCR1
register
and
RSPEN
in the
SPORT_RCR1
register, respectively). Each method has a
different effect on the SPORT.
A processor reset disables the SPORTs by clearing the
SPORT_TCR1
,
SPORT_TCR2
,
SPORT_RCR1
, and
SPORT_RCR2
registers (including the
TSPEN
and
RSPEN
enable bits) and the
SPORT_TCLKDIV
,
SPORT_RCLKDIV
,
SPORT_TFSDIVx
, and
SPORT_RFSDIVx
clock and frame sync divisor registers.
Any ongoing operations are aborted.