ADSP-BF59x Blackfin Processor Hardware Reference
16-1
16 SYSTEM RESET AND
BOOTING
This document contains material that is subject to change without notice.
The content of the boot ROM as well as hardware behavior may change
across silicon revisions. See the anomaly list for differences between silicon
revisions. This document describes functionality of silicon revision 0.0 of
the ADSP-BF59x processors.
Overview
When the
RESET
input signal releases, the processor examines the state of
the boot mode select pins (
BMODE2–0
) to determine the starting address for
instruction execution. Based on the settings of these pins, instruction exe-
cution starts from either the base address of L1 ROM or the base address
of Boot ROM.
The internal boot ROM includes a small boot kernel that loads applica-
tion data from an external memory or host device. The application data is
expected to be available in a well-defined format called the boot stream. A
boot stream consists of multiple blocks of data and special commands that
instruct the boot kernel how to initialize on-chip L1 memories as well as
off-chip volatile memories.
The boot kernel processes the boot stream block-by-block until it is
instructed by a special command to terminate the procedure and jump to
the application’s programmable start address, which traditionally is at
0xFFA0 0000 in on-chip L1 memory. This process is called “booting.”
Summary of Contents for ADSP-BF59x Blackfin
Page 64: ...Development Tools 1 22 ADSP BF59x Blackfin Processor Hardware Reference...
Page 74: ...Processor Specific MMRs 2 10 ADSP BF59x Blackfin Processor Hardware Reference...
Page 244: ...Programming Examples 6 40 ADSP BF59x Blackfin Processor Hardware Reference...
Page 700: ...Programming Examples 16 78 ADSP BF59x Blackfin Processor Hardware Reference...
Page 738: ...Boundary Scan Architecture B 8 ADSP BF59x Blackfin Processor Hardware Reference...