Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 101 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 5-1
5 DIRECT MEMORY ACCESS
This chapter describes the direct memory access (DMA) controller. Fol-
lowing an overview and list of key features is a description of operation
and functional modes of operation. The chapter concludes with a pro-
gramming model, consolidated register definitions, and programming
examples.
This chapter describes the features common to all the DMA channels, as
well as how DMA operations are set up. For specific peripheral features,
see the appropriate peripheral chapter for additional information. Perfor-
mance and bus arbitration for DMA operations can be found in
Chapter 3, “Chip Bus Hierarchy” .
Specific Information for the ADSP-BF59x
For details regarding the number of DMA controllers for the
ADSP-BF59x product, please refer to the
ADSP-BF592 Blackfin Processor
Data Sheet .
For DMA interrupt vector assignments, refer to Table 4-3 on page 4-17 in
Chapter 4, “System Interrupts” .
To determine how each of the DMAs is multiplexed with other functional
pins, refer to
Table 7-1 on page 7-3 through Table 7-2 on page 7-4 in
Chapter 7, “General-Purpose Ports” .
For a list of MMR addresses for each DMA, refer to Chapter A, “System
MMR Assignments” .