Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 405 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 12-7
Two Wire Interface Controller
Clock Generation and Synchronization
The TWI controller implementation only issues a clock during master
mode operation and only at the time a transfer has been initiated. If arbi-
tration for the bus is lost, the serial clock output immediately three-states.
If multiple clocks attempt to drive the serial clock line, the TWI controller
synchronizes its clock with the other remaining clocks. This is shown in
Figure 12-4 .
The TWI controller’s serial clock (
SCL
) output follows these rules:
• Once the clock high (
CLKHI
) count is complete, the serial clock out-
put is driven low and the clock low (
CLKLOW
) count begins.
• Once the clock low count is complete, the serial clock line is
three-stated and the clock synchronization logic enters into a delay
mode (shaded area) until the
SCL
line is detected at a logic 1 level.
At this time the clock high count begins.
Figure 12-3. Data Transfer With Bit Illustration
Figure 12-4. TWI Clock Synchronization
ACK MDIR
ACK = ACKNOWLEDGE
S P XMITDATA8[7:0] ACK MADDR[6:0]
P = STOP
S = START
HIGH
COUNT
LOW
COUNT
TWI CONTROLLER
CLOCK
SECOND MASTER
CLOCK
SCL
RESULT