Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 109 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 5-9
Direct Memory Access
asynchronous FIFO-style devices connected to the EBIU port. The Black-
fin processor acknowledges a DMA request by a proper number of read or
write operations. It is up to the device connected to any of the
AMSx
strobes to deassert or pulse the request signal and to decrement the num-
ber of pending requests accordingly.
Depending on HMDMA operating mode, an external DMA request may
trigger individual data word transfers or block transfers. A block can con-
sist of up to 65535 data words. For best throughput, DMA requests can
be pipelined. The HMDMA controllers feature a request counter to
decouple request timing from the data transfers.
See “Handshaked Memory DMA Operation” on page 5-36 for a func-
tional description.
Modes of Operation
The following sections describe the DMA operation.
Register-Based DMA Operation
Register-based DMA is the traditional kind of DMA operation. Software
configures the source or destination address and the length of the data to
be transferred to memory-mapped registers and then starts DMA
operation.
For basic operation, the software performs these steps:
• Write the source or destination address to the 32-bit
DMAx_START_ADDR
register.
• Write the number of data words to be transferred to the 16-bit
DMAx_X_COUNT
register.