Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 107 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 5-7
Direct Memory Access
buses. Typically, it is used to transfer data between external memory and
internal memory. It will also support DMA from the boot ROM on the
DEB bus. The FIFO can be used to hold DMA data transferred between
two L1 memory locations or between two external memory locations.
Each page of MDMA channels consists of:
• A source channel (for reading from memory)
• A destination channel (for writing to memory)
A memory-to-memory transfer always requires both the source and the
destination channel to be enabled. Each source/destination channel forms
a “stream,” and these two streams are hardwired for DMA priorities 12
through 15.
• Priority 12: MDMA0 destination
• Priority 13: MDMA0 source
• Priority 14: MDMA1 destination
• Priority 15: MDMA1 source
MDMA0 takes precedence over MDMA1, unless round-robin scheduling
is used or priorities become urgent, as programmed by the
DRQ
bit field in
the
HMDMA_CONTROL
register.

It is illegal to program a source channel for memory write or a des-
tination channel for memory read.
The channels support 8-, 16-, and 32-bit memory DMA transfers, but
both ends of the MDMA connect to 16-bit buses. Source and destination
channels must be programmed to the same word size. In other words, the
MDMA transfer does not perform packing or unpacking of data; each
read results in one write. Both ends of the MDMA FIFO for a given
stream are granted priority at the same time. Each pair shares an 8-word
deep 16-bit FIFO. The source DMA engine fills the FIFO, while the