Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 490 / 772

SPI Registers
13-36 ADSP-BF59x Blackfin Processor Hardware Reference
Figure 13-13. SPI Control Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
0
TIMOD[1:0] (Transfer Initiation
Mode)
00 - Start transfer with read of
SPI_RDBR, interrupt when
SPI_RDBR is full
01 - Start transfer with write of
SPI_TDBR, interrupt when
SPI_TDBR is empty
10 - Start transfer with DMA read
of SPI_RDBR, request further
DMA reads as long as SPI DMA
FIFO is not empty
11 - Start transfer with DMA write
of SPI_TDBR, request further
DMA writes as long as SPI DMA
FIFO is not full
S Z ( S end Zero)
Send zero or last word when
SPI_TDBR is empty
0 - Send last word
1 - Send zeros
GM (Get More Data)
When SPI_RDBR is full, get
data or discard incoming data
0 - Discard incoming data
1 - Get more data, overwrite
previous data
P SS E ( S lave S elect Enable)
0 - Disable
1 - Enable
EMI S O (Enable MI S O)
0 - MISO disabled
1 - MISO enabled
Reset = 0x0400
S PE ( S PI Enable)
0 - Disabled
1 - Enabled
WOM (Write Open Drain
Master)
0 - Normal
1 - Open drain
M S TR (Master)
Sets the SPI module as
master or slave
0 - Slave
1 - Master
CPOL (Clock Polarity)
0 - Active high SCK
1 - Active low SCK
CPHA (Clock Phase)
Selects transfer format and
operation mode
0 - SCK toggles from middle
of the first data bit, slave select
pins controlled by hardware
1 - SCK toggles from beginning
of first data bit, slave select
pins controlled by software
L S BF (L S B First)
0 - MSB sent/received first
1 - LSB sent/received first
S IZE ( S ize of Words)
0 - 8 bits
1 - 16 bits
S PI Control Register ( S PI_CTL)