Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 540 / 772

Functional Description
14-34 ADSP-BF59x Blackfin Processor Hardware Reference
In Figure 14-11 on page 14-34 ,
TCKFE
=
RCKFE
= 1 and transmit and
receive are connected together to share the same clock and frame syncs.
Early Versus Late Frame Syncs (Normal Versus
Alternate Timing)
Frame sync signals can occur during the first bit of each data word (late)
or during the serial clock cycle immediately preceding the first bit (early).
The
LATFS
and
LARFS
bits of the
SPORT_TCR1
and
SPORT_RCR1
registers con-
figure this option.
When
LATFS
= 0 or
LARFS
= 0, early frame syncs are configured; this is the
normal mode of operation. In this mode, the first bit of the transmit data
word is available and the first bit of the receive data word is sampled in the
serial clock cycle after the frame sync is asserted, and the frame sync is not
checked again until the entire word has been transmitted or received. In
multichannel operation, this corresponds to the case when multichannel
frame delay is 1.
If data transmission is continuous in early framing mode (in other words,
the last bit of each word is immediately followed by the first bit of the next
word), then the frame sync signal occurs during the last bit of each word.
Internally generated frame syncs are asserted for one clock cycle in early
framing mode. Continuous operation is restricted to word sizes of 4 or
longer (
SLEN
≥
3).
Figure 14-11. Example of TCKFE = RCKFE = 1, Transmit and Receive
Connected
B1 B2 B3
TSCLK = RSCLK
INTERNAL OR EXTERNAL
TFS = RFS
INTERNAL OR EXTERNAL
DT B0
B1 B2 B3 DR B0
DRIVE
EDGE SAMPLE
EDGE