Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 188 / 772

DMA Registers
5-88 ADSP-BF59x Blackfin Processor Hardware Reference
DMA Traffic Control Registers
(DMA_TC_PER and DMA_TC_CNT)
The
DMA_TC_PER
register (see Figure 5-25 ) and the
DMA_TC_CNT
register (see
Figure 5-26 ) work with other DMA registers to define traffic control.
DMA_TC_PER Register
DMA_TC_CNT Register
The
MDMA_ROUND_ROBIN_COUNT
field shows the current transfer count
remaining in the MDMA round-robin period. It initializes to
MDMA_ROUND_ROBIN_PERIOD
whenever
DMA_TC_PER
is written, whenever a
different MDMA stream is granted, or whenever every MDMA stream is
idle. It then counts down to 0 with each MDMA transfer. When this
count decrements from 1 to 0, the next available MDMA stream is
selected.
Figure 5-25. DMA Traffic Control Counter Period Register
0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0
Maximum length of MDMA round
robin bursts. If not zero, any MDMA
stream which receives a grant is
allowed up to that number of DMA
transfers, to the exclusion of the other
MDMA streams.
DMA Traffic Control Counter Period Register (DMA_TC_PER)
DAB_TRAFFIC_PERIOD[2:0]
000 - No DAB bus transfer grouping performed
Other - Preferred length of unidirectional bursts
on the DAB bus between the DMA and the
peripherals
MDMA_ROUND_ROBIN_PERIOD[4:0]
DCB_TRAFFIC_PERIOD[ 3 :0]
DEB_TRAFFIC_PERIOD[ 3 :0]
Reset = 0x0000
0000 - No DCB bus transfer
grouping performed
Other - Preferred length of unidi-
rectional bursts on the DCB bus
between the DMA and internal L1
memory
0000 - No DEB bus transfer
grouping performed
Other - Preferred length of unidi-
rectional bursts on the DEB bus
between the DMA and external
memory