Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 411 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 12-13
Two Wire Interface Controller
3. Program
TWI_FIFO_CTL
. Indicate if transmit FIFO buffer interrupts
should occur with each byte transmitted (8-bits) or with each two
bytes transmitted (16-bits).
4. Program
TWI_INT_MASK
. Enable bits associated with the desired
interrupt sources. As an example, programming the value 0x0030
results in an interrupt output to the processor in the event that the
master transfer completes, and the master transfer has an error.
5. Program
TWI_MASTER_CTL
. Ultimately this prepares and enables
master mode operation. As an example, programming the value
0x0201 enables master mode operation, generates a 7-bit address,
sets the direction to master-transmit, uses standard mode timing,
and transmits 8 data bytes before generating a Stop condition.
Table 12-3 shows what the interaction between the TWI controller and
the processor might look like using this example.
Table 12-3. Master Mode Transmit Setup Interaction
TWI Controller Master Processor
Interrupt: XMTEMPTY – Transmit buffer is
empty. Write transmit FIFO buffer.
Acknowledge: Clear interrupt source bits.
... ...
Interrupt: MCOMP – Master transfer com-
plete. Acknowledge: Clear interrupt source bits.