Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 168 / 772

DMA Registers
5-68 ADSP-BF59x Blackfin Processor Hardware Reference
The fields of the
DMAx_CONFIG
register are used to set up DMA parameters
and operating modes.
•
FLOW[2:0]
(next operation). This field specifies the type of DMA
transfer to follow the present one. The flow options are:
• 0x0 - stop. When the current work unit completes, the DMA chan-
nel stops automatically, after signaling an interrupt (if selected).
The
DMA_RUN
status bit in the
DMAx_IRQ_STATUS
register changes
from 1 to 0, while the
DMAEN
bit in the
DMAx_CONFIG
register is
unchanged. In this state, the channel is paused. Peripheral
interrupts are still filtered out by the DMA unit. The channel may
be restarted simply by another write to the
DMAx_CONFIG
register
specifying the next work unit, in which the
DMAEN
bit is set to 1.
0x1 - autobuffer mode. In this mode, no descriptors in memory are
used. Instead, DMA is performed in a continuous circular buffer
fashion based on user-programmed DMA MMR settings. Upon
completion of the work unit, the parameter registers are reloaded
into the current registers, and DMA resumes immediately with
zero overhead. Autobuffer mode is stopped by a user write of 0 to
the
DMAEN
bit in the
DMAx_CONFIG
register.
0x4 - descriptor array mode. This mode fetches a descriptor from
memory that does not include the
NDPH
or
NDPL
elements. Because
the descriptor does not contain a next descriptor pointer entry, the
DMA engine defaults to using the
DMAx_CURR_DESC_PTR
register to
step through descriptors, thus allowing a group of descriptors to
follow one another in memory like an array.
0x6 - descriptor list (small model) mode. This mode fetches a
descriptor from memory that includes
NDPL
, but not
NDPH
. There-
fore, the high 16 bits of the next descriptor pointer field are taken
from the upper 16 bits of the
DMAx_NEXT_DESC_PTR
register, thus
confining all descriptors to a specific 64K page in memory.