Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 177 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 5-77
Direct Memory Access
DMA Inner Loop Address Increment Registers
(DMAx_X_MODIFY/MDMA_yy_X_MODIFY)
The
DMAx_X_MODIFY
register, shown in Figure 5-12 , contains a signed,
two’s-complement byte-address increment. In 1-D DMA, this increment
is the stride that is applied after transferring each element.

DMAx_X_MODIFY
is specified in bytes, regardless of the DMA transfer
size.
In 2-D DMA, this increment is applied after transferring each element in
the inner loop, up to but not including the last element in each inner
loop. After the last element in each inner loop, the
DMAx_Y_MODIFY
register
is applied instead, except on the very last transfer of each work unit. The
DMAx_X_MODIFY
register is always applied to the last transfer of a work unit.
The
DMAx_X_MODIFY
field may be set to 0. In this case, DMA is performed
repeatedly to or from the same address. This is useful, for example, in
transferring data between a data register and an external memory-mapped
peripheral.
Figure 5-12. DMA Inner Loop Address Increment Registers
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X
X_MODIFY[15:0] (Inner
Loop Address Increment)
X X X X X X X X X X X X X X X
DMA Inner Loop Address Increment Registers (DMAx_X_MODIFY/MDMA_yy_X_MODIFY)
R/W prior to enabling channel; RO after enabling channel
Reset = Undefined
Stride (in bytes) to take after
each decrement of
CURR_X_COUNT