Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual

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ADSP-BF59x Blackfin Processor Hardware Reference 12-39
Two Wire Interface Controller
[11] The FIFO is full and contains two bytes of data. Either a sin-
gle or double byte peripheral read of the FIFO is allowed.
• Transmit FIFO status (
XMTSTAT[1:0]
)
The
XMTSTAT
field is read only. It indicates the number of valid data
bytes in the FIFO buffer. The status is updated with each FIFO
buffer write using the peripheral data bus or read access by the
transmit shift register. Simultaneous accesses are allowed.
[00] The FIFO is empty. Either a single or double byte peripheral
write of the FIFO is allowed.
[01] The FIFO contains one byte of data. A single byte peripheral
write of the FIFO is allowed.
[10] Reserved
[11] The FIFO is full and contains two bytes of data.
TWI Interrupt Mask Register (TWI_INT_MASK)
The
TWI_INT_MASK
register enables interrupt sources to assert the interrupt
output. Each mask bit corresponds with one interrupt source bit in the
TWI_INT_STAT
register. Reading and writing the
TWI_INT_MASK
register
does not affect the contents of the
TWI_INT_STAT
register.