Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 628 / 772

Reset and Power-up
16-6 ADSP-BF59x Blackfin Processor Hardware Reference
Reset Vector
When reset releases, the processor starts fetching and executing instruc-
tions from
either address 0xEF00 0000 or 0xFFA1 0000, based on the
settings of boot mode select pins.
On a hardware reset, the boot kernel initializes the
EVT1
register to
0xFFA0 0000. When the booting process completes, the boot kernel
jumps to the location provided by the
EVT1
vector register. The content of
the
EVT1
register is overwritten by the
TARGET ADDRESS
field of the first
block of the applied boot stream. If the
BCODE
field of the
SYSCR
register is
set to 3 (no boot option), the
EVT1
register is not modified by the boot
kernel on software resets. Therefore, programs can control the reset vector
for software resets through the
EVT1
register. This process is illustrated by
the flow chart in Figure 16-1 .
The content of the
EVT1
register may be undefined in emulator sessions.
Servicing Reset Interrupts
The processor services a reset event like other interrupts. The reset inter-
rupt has top priority. Only emulation events have higher priority. When
coming out of reset, the processor is in supervisor mode and has full access
to all system resources. The boot kernel can be seen as part of the reset ser-
vice routine. It runs at the top interrupt priority level.
Even when the boot process has finished and the boot kernel passes con-
trol to the user application, the processor is still in the reset interrupt. To
enter user mode, the reset service routine must initialize the
RETI
register
and terminate with an
RTI
instruction.
For a programming example, see “System Reset” on page 16-71 .
Listing 16-1 and Listing 16-2 on page 16-72 show code examples that
handle the reset event. See the Blackfin Processor Programming Reference
for details on user and supervisor modes.