Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 406 / 772

Description of Operation
12-8 ADSP-BF59x Blackfin Processor Hardware Reference
Bus Arbitration
The TWI controller initiates a master mode transmission (
MEN
) only when
the bus is idle. If the bus is idle and two masters initiate a transfer, arbitra-
tion for the bus begins. This is shown in
Figure 12-5 .
The TWI controller monitors the serial data bus (SDA) while
SCL
is high
and if SDA is determined to be an active logic 0 level while the TWI con-
troller’s data is a logic 1 level, the TWI controller has lost arbitration and
ends generation of clock and data. Note arbitration is not performed only
at serial clock edges, but also during the entire time
SCL
is high.
Start and Stop Conditions
Start and stop conditions involve serial data transitions while the serial
clock is a logic 1 level. The TWI controller generates and recognizes these
transitions. Typically start and stop conditions occur at the beginning and
at the conclusion of a transmission with the exception repeated start
“combined” transfers, as shown in
Figure 12-6 .
Figure 12-5. TWI Bus Arbitration
START
SCL (BUS)
TWI CONTROLLER
DATA
SECOND MASTER
DATA
SDA (BUS)
ARBITRATION
LOST