Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 364 / 772

Description of Operation
11-8 ADSP-BF59x Blackfin Processor Hardware Reference
situations are detected. Every error has an indicating bit in the
UART_LSR
register.
• Overrun error (
OE
bit)
• Parity error (
PE
bit)
• Framing error/Invalid stop bit (
FE
bit)
• Break indicator (
BI
bit)
Reception is started when a falling edge is detected on the RX input pin.
The receiver attempts to see a start bit. For better immunity against noise
and hazards on the line, the receiver oversamples every bit 16 times and
does a majority decision based on the middle three samples. The data is
shifted immediately into the internal
RSR
register. After the 9th sample of
the first stop bit is processed, the received data is copied to the
UART_RBR
register and the receiver recovers itself for further data.
The sampling clock, equal to 16 times the bit rate, samples the data bits
close to their midpoint. Because the receiver clock is usually asynchronous
to the transmitter’s data rate, the sampling point may drift relative to the
center of the data bits. The sampling point is synchronized again with
each start bit, so the error accumulates only over the length of a single
word. A receive filter removes spurious pulses of less than two times the
sampling clock period.
IrDA Transmit Operation
To generate the IrDA pulse transmitted by the UART, the normal NRZ
output of the transmitter is first inverted if the
TPOLC
bit is cleared, so a 0
is transmitted as a high pulse of 16 UART clock periods and a 1 is trans-
mitted as a low pulse for 16 UART clock periods. The leading edge of the
pulse is then delayed by six UART clock periods. Similarly, the trailing
edge of the pulse is truncated by eight UART clock periods. This results in
the final representation of the original 0 as a high pulse of only 3 clock