Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 585 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 15-1
15 PARALLEL PERIPHERAL
INTERFACE
This chapter describes the parallel peripheral interface (PPI). Following an
overview and a list of key features are a description of operation and func-
tional modes of operation. The chapter concludes with a programming
model, consolidated register definitions, and programming examples.
Specific Information for the ADSP-BF59x
For details regarding the number of PPIs for the ADSP-BF59x product,
please refer to the
ADSP-BF592 Blackfin Processor Data Sheet .
For PPI DMA channel assignments, refer to Table 5-9 on page 5-103 in
Chapter 5, “Direct Memory Access” .
For PPI interrupt vector assignments, refer to Table 4-3 on page 4-17 in
Chapter 4, “System Interrupts” .
To determine how each of the PPIs is multiplexed with other functional
pins, refer to
Table 7-1 on page 7-3 through Table 7-2 on page 7-4 in
Chapter 7, “General-Purpose Ports” .
For a list of MMR addresses for each PPI, refer to Chapter A, “System
MMR Assignments” .
PPI behavior for the ADSP-BF59x that differs from the general informa-
tion in this chapter can be found in the section
“Unique Information for
the ADSP-BF59x Processor” on page 15-37