Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 382 / 772

UART Registers
11-26 ADSP-BF59x Blackfin Processor Hardware Reference
UART Receive Buffer (UART_RBR) Register
The read-only
UART_RBR
register, shown in Figure 11-11 , is mapped to the
same address as the write-only
UART_THR
and
UART_DLL
registers. To access
UART_RBR
, the
DLAB
bit in
UART_LCR
must be cleared. When the
DLAB
bit is
cleared, writes to this address target the
UART_THR
register, while reads
from this address return the value in the
UART_RBR
register.
UART Interrupt Enable (UART_IER) Register
The
UART_IER
register, shown in Figure 11-12 on page 11-27 , is used to
enable requests for system handling of empty or full states of UART data
registers. Unless polling is used as a means of action, the
ERBFI
and/or
ETBEI
bits in this register are normally set.
Setting this register without enabling system DMA causes the UART to
notify the processor of data inventory state by means of interrupts. For
proper operation in this mode, system interrupts must be enabled, and
Figure 11-10. UART Transmit Holding Register
Figure 11-11. UART Receive Buffer Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Transmit Hold[7:0]
UART Transmit Holding Register (UART_THR)
write only
Reset = 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Receive Buffer[7:0]
UART Receive Buffer Register (UART_RBR)
read only
Reset = 0x0000