Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 70 / 772

Processor-Specific MMRs
2-6 ADSP-BF59x Blackfin Processor Hardware Reference
ITEST_COMMAND Register
The instruction test command register (
ITEST_COMMAND
), shown in
Figure 2-3 , contains control bits for the L1 data memory.
This register may be used to gain access to the 16K bytese of L1 instruc-
tion SRAM from address 0xFFA04000 to address 0xFFA07FFF. All other
regions of L1 memory—both data and instruction—are accessed using the
DTEST_COMMAND
register.
Figure 2-3. Instruction Test Command Register
X
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
X X X X X X X X X X X X X X X
Instruction Test Command Register (ITE S T_COMMAND)
Address bits [13:12]
ADR[1 3 :12]
Reset = Undefined
Read/Write Access
ADR[11:10]
Address bits [11:10]
0 - Read access
1 - Write access
Reserved - Write 1
ADR[9: 3 ]
Address bits [9:3]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X X X X X X X X X X X X X X X X
0xFFE0 1 3 00