Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 561 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 14-55
SPORT Controller
• Low receive frame sync select . (
LRFS
). This bit selects an active low
RFS
(if set) or active high
RFS
(if cleared).
• Late receive frame sync . (
LARFS
). This bit configures late frame
syncs (if set) or early frame syncs (if cleared).
• Clock drive/sample edge select . (
RCKFE
). This bit selects which
edge of the
RSCLK
clock signal the SPORT uses for sampling data,
for sampling externally generated frame syncs, and for driving
internally generated frame syncs. If set, internally generated frame
syncs are driven on the falling edge, and data and externally gener-
ated frame syncs are sampled on the rising edge. If cleared,
internally generated frame syncs are driven on the rising edge, and
data and externally generated frame syncs are sampled on the fall-
ing edge.
• RxSec enable . (
RXSE
). This bit enables the receive secondary side of
the SPORT (if set).
• Stereo serial enable . (
RSFSE
). This bit enables the stereo serial oper-
ating mode of the SPORT (if set). By default this bit is cleared,
enabling normal clocking and frame sync.
• Left/Right order . (
RRFST
). If this bit is set, the right channel is
received first in stereo serial operating mode. By default this bit is
cleared, and the left channel is received first.
Data Word Formats
The format of the data words transferred over the SPORTs is configured
by the combination of transmit
SLEN
and receive
SLEN; RDTYPE
;
TDTYPE
;
RLSBIT
; and
TLSBIT
bits of the
SPORT_TCR1
,
SPORT_TCR2
,
SPORT_RCR1
, and
SPORT_RCR2
registers.