Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 717 / 772

ADSP-BF59x Blackfin Processor Hardware Reference A-7
System MMR Assignments
Ports Registers
Ports registers (port F: 0xFFC0 0700 – 0xFFC0 07FF, port G:
0xFFC0 1500 – 0xFFC0 15FF, port H: 0xFFC0 1700 – 0xFFC0 17FF,
pin control: 0xFFC0 3200 – 0xFFC0 32FF) are listed in
Table A-8 .
Table A-8. Ports Registers
Memory-Mapped
Address Register Name For individual bits, see this diagram:
0xFFC0 0700 PORTFIO “GPIO Data Registers” on page 7-23
0xFFC0 0704 PORTFIO_CLEAR “GPIO Clear Registers” on page 7-24
0xFFC0 0708 PORTFIO_SET “GPIO Set Registers” on page 7-24
0xFFC0 070C PORTFIO_TOGGLE “GPIO Toggle Registers” on page 7-25
0xFFC0 0710 PORTFIO_MASKA “GPIO Mask Interrupt A Registers” on
page 7-27
0xFFC0 0714 PORTFIO_MASKA_CLEAR “GPIO Mask Interrupt A Clear Registers”
on page 7-30
0xFFC0 0718 PORTFIO_MASKA_SET “GPIO Mask Interrupt A Set Registers” on
page 7-28
0xFFC0 071C PORTFIO_MASKA_TOGGLE “GPIO Mask Interrupt A Toggle Registers”
on page 7-32
0xFFC0 0720 PORTFIO_MASKB “GPIO Mask Interrupt B Registers” on
page 7-27
0xFFC0 0724 PORTFIO_MASKB_CLEAR “GPIO Mask Interrupt B Clear Registers”
on page 7-31
0xFFC0 0728 PORTFIO_MASKB_SET “GPIO Mask Interrupt B Set Registers” on
page 7-29
0xFFC0 072C PORTFIO_MASKB_TOGGLE “GPIO Mask Interrupt B Toggle Registers”
on page 7-33
0xFFC0 0730 PORTFIO_DIR “GPIO Direction Registers” on page 7-22
0xFFC0 0734 PORTFIO_POLAR “GPIO Polarity Registers” on page 7-25