Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 427 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 12-29
Two Wire Interface Controller
This bit self clears if slave mode is disabled (
SEN
= 0).
[0] At the time of addressing, the address was not determined to be
a general call.
[1] At the time of addressing, the address was determined to be a
general call.
• Slave transfer direction (
SDIR
)
This bit self clears if slave mode is disabled (
SEN
= 0).
[0] At the time of addressing, the transfer direction was determined
to be slave receive.
[1] At the time of addressing, the transfer direction was determined
to be slave transmit.
TWI Master Mode Control Register
(TWI_MASTER_CTL)
The
TWI_MASTER_CTL
register controls the logic associated with master
mode operation. Bits in this register do not affect slave mode operation
and should not be modified to control slave mode functionality.
Figure 12-19. TWI Master Mode Control Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TWI Master Mode Control Register (TWI_MA S TER_CTL)
Reset = 0x0000
MEN (Master Mode Enable)
MDIR (Master Transfer
Direction)
S DAOVR ( S erial
Data Override)
S CLOVR ( S erial
Clock Override)
DCNT[7:0] (Data
Transfer Count)
FA S T (Fast Mode)
S TOP (Issue S top
Condition)
R S TART (Repeat S tart)