Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 131 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 5-31
Direct Memory Access
DMA Control Commands
Advanced peripherals, such as an Ethernet MAC module, are capable of
managing some of their own DMA operations, thus dramatically improv-
ing real-time performance and relieving control and interrupt demands on
the Blackfin processor core. These peripherals may communicate to the
DMA controller using DMA control commands, which are transmitted
from the peripheral to the associated DMA channel over internal DMA
request buses. Refer to
“Unique Information for the ADSP-BF59x Proces-
sor” on page 5-101 to determine if DMA control commands are
applicable to a particular product.
The request buses consist of three wires per DMA-management-capable
peripheral. The DMA control commands extend the set of operations
available to the peripheral beyond the simple “request data” command
used by peripherals in general.
While these DMA control commands are not visible to or controllable by
the user, their use by a peripheral has implications for the structure of the
DMA transfers which that peripheral can support. It is important that
application software be written to comply with certain restrictions regard-
ing work units and descriptor chains (described later in this section) so
that the peripheral operates properly whenever it issues DMA control
commands.
Table 5-2. Legal NDSIZE Values
FLOW NDSIZE Note
0 0
1 0
4
0 < NDSIZE
≤
7
Descriptor array, no descriptor pointer fetched
6
0 < NDSIZE
≤
8
Descriptor list, small descriptor pointer fetched
7
0 < NDSIZE
≤
9
Descriptor list, large descriptor pointer fetched