Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 369 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 11-13
UART Port Controllers
Table 11-1 provides example divide factors required to support most stan-
dard baud rates.

Careful selection of
SCLK
frequencies, that is, even multiples of
desired bit rates, can result in lower error percentages.
Note that the UART module is clocked 16 times faster than the bit clock.
This is required to oversample bits on reception and to generate RZI code
in IrDA mode.
Autobaud Detection
At the chip level, the UART RX pin is routed to the alternate capture
input (
TACIx
) of a general purpose timer. When working in
WDTH_CAP
mode this timer can be used to automatically detect the bit rate applied to
the
RX
pin by an external device. For more information, see Chapter 7,
“General-Purpose Ports” .
The capture capabilities of the timers are often used to supervise the bit
rate at runtime. If the Blackfin UART talks to a device supplied by a weak
Table 11-1. UART Bit Rate Examples With 100 MHz SCLK
Bit Rate
DL Actual % Error
2400 2604 2400.15 0.006
4800 1302 4800.31 0.007
9600 651 9600.61 0.006
19200 326 19171.78 0.147
38400 163 38343.56 0.147
57600 109 57339.45 0.452
115200 54 115740.74 0.469
921600 7 892857.14 3.119
6250000 1 6250000 –