Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 428 / 772

Register Descriptions
12-30 ADSP-BF59x Blackfin Processor Hardware Reference
Additional information for the
TWI_MASTER_CTL
register bits includes:
• Serial clock override (
SCLOVR
)
This bit can be used when direct control of the serial clock line is
required. Normal master and slave mode operation should not
require override operation.
[0] Normal serial clock operation under the control of master
mode clock generation and slave mode clock stretching logic.
[1] Serial clock output is driven to an active 0 level overriding all
other logic. This state is held until this bit is cleared.
• Serial data (SDA) override (
SDAOVR
)
This bit can be used when direct control of the serial data line is
required. Normal master and slave mode operation should not
require override operation.
[0] Normal serial data operation under the control of the transmit
shift register and acknowledge logic.
[1] Serial data output is driven to an active 0 level overriding all
other logic. This state is held until this bit is cleared.
• Data transfer count (
DCNT[7:0]
)
Indicates the number of data bytes to transfer. As each data word is
transferred,
DCNT
is decremented. When
DCNT
is 0, a stop condition
is generated. Setting
DCNT
to 0xFF disables the counter. In this
transfer mode, data continues to be transferred until it is concluded
by setting the
STOP
bit.
• Repeat start (
RSTART
)
[0] Transfer concludes with a stop condition.