Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 464 / 772

Interface Overview
13-10 ADSP-BF59x Blackfin Processor Hardware Reference
FIFO will be empty. When the
SPIF
bit subsequently gets set, the
last word has been transferred and the SPI can be disabled or
enabled for another mode.
Internal Interfaces
The SPI has dedicated connections to the processor’s peripheral bus (PAB)
and DAB.
The low-latency PAB bus is used to map the SPI resources into the system
MMR space. For PAB accesses to SPI MMRs, the primary performance
criteria is latency, not throughput. Transfer latencies for both read and
write transfers on the peripheral bus are two
SCLK
cycles.
The DAB bus provides a means for DMA SPI transfers to gain access to
on-chip and off-chip memory with little or no degradation in core band-
width to memory. The SPI peripheral, as a DMA master, is capable of
sourcing DMA accesses. The arbitration policy for access to the DAB is
described in the
Chip Bus Hierarchy chapter.
DMA Functionality
The SPI has a single DMA engine which can be configured to support
either an SPI transmit channel or a receive channel, but not both simulta-
neously. Therefore, when configured as a transmit channel, the received
data will essentially be ignored.
When configured as a receive channel, what is transmitted is irrelevant. A
16-bit by four-word FIFO (without burst capability) is included to
improve throughput on the DAB.

When using DMA for SPI transmit, the
DMA_DONE
interrupt signi-
fies that the DMA FIFO is empty. However, at this point there
may still be data in the SPI DMA FIFO waiting to be transmitted.
Therefore, software needs to poll
TXS
in the
SPI_STAT
register until
it goes low for two successive reads, at which point the SPI DMA