Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 393 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 11-37
UART Port Controllers
Note that polling the
UART0_LSR
register for transmit purposes may clear
the receive error latch bits. It is, therefore, not recommended to poll
UART0_LSR
for transmission this way while data is being received. In that
case, write a polling loop that reads
UART_LSR
once and then evaluates all
status bits of interest, as shown in Listing 11-6 .
Listing 11-6. UART Polling Loop
uart_loop:
r7 = w[p0+UART0_LSR-UART0_GCTL] (z);
CC = bittst(r7, bitpos(DR));
if !CC jump uart_loop.transmit;
r6 = w[p0+UART0_RBR-UART0_GCTL] (z);
r5 = BI | OE | FE | PE (z);
r5 = r5 & r7;
CC = r5 == 0;
if !CC jump uart_loop.error;
b[p1++] = r6; /* store byte */
uart_loop.transmit:
CC = bittst(r7, bitpos(THRE));
if !CC jump uart_loop;
r5 = b[p2++] (z); /* load next byte */
w[p0+UART0_THR-UART0_GCTL] = r5;
jump uart_loop;
uart_loop.error:
...
jump uart_loop;
In non-DMA interrupt operation, the three UART interrupt request lines
may or may not be ORed together in the system interrupt controller. If
they had three different service routines, they may look as shown in
Listing 11-7 .