Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 557 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 14-51
SPORT Controller
• Late transmit frame sync . (
LATFS
). This bit configures late frame
syncs (if set) or early frame syncs (if cleared).
• Clock drive/sample edge select . (
TCKFE
). This bit selects which
edge of the
TCLKx
signal the SPORT uses for driving data, for driv-
ing internally generated frame syncs, and for sampling externally
generated frame syncs. If set, data and internally generated frame
syncs are driven on the falling edge, and externally generated frame
syncs are sampled on the rising edge. If cleared, data and internally
generated frame syncs are driven on the rising edge, and externally
generated frame syncs are sampled on the falling edge.
• TxSec enable . (
TXSE
). This bit enables the transmit secondary side
of the SPORT (if set).
• Stereo serial enable . (
TSFSE
). This bit enables the stereo serial oper-
ating mode of the SPORT (if set). By default this bit is cleared,
enabling normal clocking and frame sync.
• Left/Right order . (
TRFST
). If this bit is set, the right channel is
transmitted first in stereo serial operating mode. By default this bit
is cleared, and the left channel is transmitted first.
SPORT Receive Configuration
(SPORT_RCR1 and SPORT_RCR2) Registers
The main control registers for the receive portion of each SPORT are the
receive configuration registers,
SPORT_RCR1
and
SPORT_RCR2
, shown in
Figure 14-27 on page 14-52 and Figure 14-28 on page 14-53 .
A SPORT is enabled for receive if bit 0 (
RSPEN
) of the receive configura-
tion 1 register is set to 1. This bit is cleared during either a hard reset or a
soft reset, disabling all SPORT reception.