Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 498 / 772

Programming Examples
13-44 ADSP-BF59x Blackfin Processor Hardware Reference
Initialization Sequence
Before the SPI can transfer data, the registers must be configured as
follows.
Listing 13-1. SPI Register Initialization
SPI_Register_Initialization:
P0.H = hi(SPI_FLG);
P0.L = lo(SPI_FLG);
R0 = W[P0] (Z);
BITSET (R0,0x7); /* FLS7 */
W[P0] = R0; /* Enable slave-select output pin */
P0.H = hi(SPI_BAUD);
P0.L = lo(SPI_BAUD);
R0.L = 0x208E; /* Write to SPI Baud rate register */
W[P0] = R0.L; ssync; /* If SCLK = 133 MHz, SPI clock ~= 8 kHz
*/
/* Setup SPI Control Register */
/*************************************************
* TIMOD [1:0] = 00 : Transfer On RDBR Read.
* SZ [2] = 0 : Send Last Word When TDBR Is Empty
* GM [3] = 1 : Overwrite Previous Data If RDBR Is Full
* PSSE [4] = 0 : Disables Slave-Select As Input (Master)
* EMISO [5] = 0 : MISO Disabled For Output (Master)
* [7] and [6] = 0 : RESERVED
* SIZE [8] = 1 : 16 Bit Word Length Select
* LSBF [9] = 0 : Transmit MSB First
* CPHA [10] = 0 : Hardware Controls Slave-Select Outputs
* CPOL [11] = 1 : Active Low SCK
* MSTR [12] = 1 : Device Is Master
* WOM [13] = 0 : Normal MOSI/MISO Data Output (No Open Drain)
* SPE [14] = 1 : SPI Module Is Enabled