Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 124 / 772

Functional Description
5-24 ADSP-BF59x Blackfin Processor Hardware Reference
current registers from the start registers:
DMAx_CURR_ADDR
loaded from
DMAx_START_ADDR
DMAx_CURR_X_COUNT
loaded from
DMAx_X_COUNT
DMAx_CURR_Y_COUNT
loaded from
DMAx_Y_COUNT
The
DFETCH
bit in the
DMAx_IRQ_STATUS
register is then cleared,
after which the DMA transfer begins again, as shown in Figure 5-2
on page 5-19 .
Work Unit Transitions
Transitions from one work unit to the next are controlled by the
SYNC
bit
in the
DMAx_CONFIG
register of the work units. In general, continuous tran-
sitions have lower latency at the cost of restrictions on changes of data
format or addressed memory space in the two work units. These latency
gains and data restrictions arise from the way the DMA FIFO pipeline is
handled while the next descriptor is fetched. In continuous transitions
(
SYNC
= 0), the DMA FIFO pipeline continues to transfer data to and
from the peripheral or destination memory during the descriptor fetch
and/or when the DMA channel is paused between descriptor chains.
Synchronized transitions (
SYNC
= 1), on the other hand, provide better
real-time synchronization of interrupts with peripheral state and greater
flexibility in the data formats and memory spaces of the two work units, at
the cost of higher latency in the transition. In synchronized transitions,
the DMA FIFO pipeline is drained to the destination or flushed (RX data
discarded) between work units.

Work unit transitions for MDMA streams are controlled by the
SYNC
bit of the MDMA source channel’s
DMAx_CONFIG
register. The
SYNC
bit of the MDMA destination channel is reserved and must be
0. In transmit (memory read) channels, the
SYNC
bit of the last
descriptor prior to the transition controls the transition behavior.
In contrast, in receive channels, the
SYNC
bit of the first descriptor
of the next descriptor chain controls the transition.