Analog Devices ADSP-BF59x Blackfin, Hardware Reference Manual, Page: 151 / 772

ADSP-BF59x Blackfin Processor Hardware Reference 5-51
Direct Memory Access
has its own distinct interrupt, interaction among the interrupts of differ-
ent peripherals is much simpler to manage.
Due to DMA FIFOs and DMA/memory pipelining, polling of the
DMAx_CURR_ADDR
,
DMAx_CURR_DESC_PTR
, or
DMAx_CURR_X_COUNT
/
DMAx_CURR_Y_COUNT
registers is not recommended for precisely synchroniz-
ing DMA with data processing. The current address, pointer, and count
registers change several cycles in advance of the completion of the corre-
sponding memory operation, as measured by the time at which the results
of the operation would first be visible to the core by memory read or write
instructions. For example, in a DMA memory write operation to external
memory, assume a DMA write by channel A is initiated that causes the
SDRAM to perform a page open operation which takes many system clock
cycles. The DMA engine may then move on to another DMA operation
by channel B which does not in itself incur latency, but will be stalled
behind the slow operation of channel A. Software monitoring of
channel B, based on examination of the
DMAx_CURR_ADDR
register contents,
would not safely conclude whether the memory location pointed to by
channel B’s
DMAx_CURR_ADDR
register has or has not been written.
If allowances are made for the lengths of the DMA/memory pipeline, poll-
ing of the current address, pointer, and count registers can permit loose
synchronization of DMA with software. The depth of the DMA FIFO is
four locations (either four 8- or 16-bit data elements, or two 32-bit data
elements) for a peripheral DMA channel, and eight locations (four 32-bit
data elements) for an MDMA FIFO. The DMA will not advance current
address/pointer/count registers if these FIFOs are filled with incomplete
work (including reads that have been started but not yet finished).
Additionally, the length of the combined DMA and L1 pipelines to inter-
nal memory is approximately six 8- or 16-bit data elements. The length of
the DMA and external bus interface unit (EBIU) pipelines is approxi-
mately three data elements, when measured from the point where a DMA
register update is visible to an MMR read to the point where DMA and
core accesses to memory become strictly ordered. If the DMA FIFO